for CharFlo-Memory! brochure.
for more characterization & verification applications.
Provide a complete solution for memory characterization
Compiled memory characterization
Customized memory characterization
"Critical-path circuit generation" modules for customers' own flow
Perform "on-the-fly" verification during characterization
Check inside the memory by recognizing structures and high-risk nets from layout-extracted netlist.
Ensure no reliability violations such as noise-margin, delay degrading, glitch, and meta-stability etc.
Validate RM (EMA) settings exhaustively by checking on-chip signals against noise-margin.
Optimize the performance of characterization process
Build complete critical-path circuits from layout-extracted netlist with RC
Execute robust RC reduction by AWE algorithms
Enable "active-net only" layout RC extraction, which reduces extraction time tremendously, and makes large-memory characterization possible.
Provide SPDM technology to reduce the table entries and characterization time.
Support varieties of models, input waveforms, and technologies
CCS timing, power and noise models.
Characterizing CCS Timing Model of Memory IP by Using CharFlo-Memory!
Ramp, exponential and Pre-driver input.
CMOS and SOI processes.
Production & silicon proven on numerous designs over years